1. Field of the Invention
The present invention relates to a semiconductor device featuring a MOS transistor, and more particularly to a semiconductor device which features a new vertical MOS transistor having a back gate electrode.
2. Description of the Background Art
As an exemplary one to achieve a variety of advantages, such as being unaffected by a latch up between adjacent MOS transistors opposite to each other in conductivity type, a semiconductor device with the MOS transistors formed individually on island-shaped thin silicon layers disposed on an insulating layer has been recently proposed.
FIG. 30 is a cross-sectional view briefly showing this kind of semiconductor device, i.e., an SOI/MOS transistor formed by the MESA isolation method. In this figure, a semiconductor substrate 30 is provided with a buried insulating layer 31 at a prescribed depth from its surface, and an island-shaped silicon layer is formed for each MOS transistor on an upper surface of the buried insulating layer 31 (this figure only shows a P-type silicon layer 32 formed by ion implantation with a P-type impurity for formation of an N-type MOS transistor and an N-type silicon layer 33 formed by ion implantation with an N-type impurity for formation of a P-type MOS transistor).
A gate electrode 34 of the N-type MOS transistor is formed on a surface of the P-type silicon layer 32, interposing a gate insulating film 35 which is formed of a silicon oxide film therebetween, and an N-type source region 36 and an N-type drain region 37 of the N-type MOS transistor are so formed as to sandwich a channel region which is positioned immediately beneath the gate electrode 34 in the P-type silicon layer 32, with their bottom surfaces in contact with the upper surface of the buried insulating layer 31. A gate electrode 38 of the P-type MOS transistor is formed on a surface of the N-type silicon layer 33, interposing a gate insulating film 39 which is formed of a silicon oxide film therebetween, and a P-type source region 40 and a P-type drain region 41 of the P-type MOS transistor are so formed as to sandwich a channel region which is positioned immediately beneath the gate electrode 38 in the N-type silicon layer 33, with their bottom surfaces in contact with the upper surface of the buried insulating layer 31.
An interlayer insulating film 42 is formed on the surface of the semiconductor substrate 30, inclusive of on the N-type MOS transistor and the P-type MOS transistor. A source electrode 43 of the N-type MOS transistor is physically and electrically connected to the source region 36 of the N-type MOS transistor through a contact hole 42a in the interlayer insulating film 42, and a drain electrode 44 of the N-type MOS transistor is physically and electrically connected to the drain region 37 of the N-type MOS transistor through a contact hole 42b in the interlayer insulating film 42.
A source electrode 45 of the P-type MOS transistor is physically and electrically connected to the source region 40 of the P-type MOS transistor through a contact hole 42c in the interlayer insulating film 42, and a drain electrode 46 of the P-type MOS transistor is physically and electrically connected to the drain region 41 of the P-type MOS transistor through a contact hole 42d in the interlayer insulating film 42.
In the semiconductor device as above constructed, the N-type MOS transistor and the P-type MOS transistor can not be individually supplied with a substrate potential, and therefore a short channel causes such a disadvantage as discussed below.
When a bottom surface of the semiconductor substrate 30 is supplied with a ground potential fixedly, if a positive potential is applied to the source region 40 of the P-type MOS transistor, a potential difference arises between the source region 40 and the semiconductor layer 30 under the buried insulating layer 31 and positive charges are collected into a portion of the bottom surface of the N-type silicon layer 33 in contact with the buried insulating layer 31 positioned between the source region 40 and the drain region 41 to raise a potential of that portion. That is apt to cause a punch through between the source region 40 and the drain region 41, and with size reduction, increases a possibility of drawing a current between the source region 40 and the drain region 41.
A solution to the above disadvantage of the P-type MOS transistor is to supply the bottom surface of the semiconductor substrate 30 with the same potential as the positive potential which is applied to the source region 40 of the P-type MOS transistor. When the bottom surface of the semiconductor substrate 30 is supplied with the positive potential fixedly, however, if the ground potential is applied to the source region 36 of the N-type MOS transistor, a potential difference arises between the source region 36 and the semiconductor layer 30 under the buried insulating layer 31 and negative charges are collected into a portion of the bottom surface of the P-type silicon layer 32 in contact with the buried insulating layer 31 positioned between the source region 36 and the drain region 37. That is apt to cause a punch through between the source region 36 and the drain region 37, and with size reduction, increases a possibility of drawing a current between the source region 36 and the drain region 37.
A solution to the above disadvantage of the N-type MOS transistor is to supply the bottom surface of the semiconductor substrate 30 with the same potential as the ground potential which is applied to the source region 36 of the N-type MOS transistor.